Download e-book for iPad: 3D Flash Memories by Rino Micheloni

By Rino Micheloni

ISBN-10: 9401775109

ISBN-13: 9789401775106

ISBN-10: 9401775125

ISBN-13: 9789401775120

This publication walks the reader during the subsequent step within the evolution of NAND flash reminiscence expertise, particularly the advance of 3D flash stories, within which a number of layers of reminiscence cells are grown in the comparable piece of silicon. It describes their operating ideas, machine architectures, fabrication recommendations and useful implementations, and highlights why 3D flash is a new technology.

After reviewing marketplace developments for either NAND and stable country drives (SSDs), the publication digs into the main points of the flash reminiscence mobilephone itself, masking either floating gate and rising cost seize applied sciences. there's a plethora of alternative fabrics and vertical integration schemes in the market. New reminiscence cells, new fabrics, new architectures (3D Stacked, BiCS and P-BiCS, 3D FG, 3D VG, 3D complex architectures); essentially, each one NAND producer has its personal resolution. bankruptcy three to bankruptcy 7 supply a wide evaluate of the way 3D can materialize. The 3D wave is impacting rising thoughts in addition and bankruptcy eight covers 3D RRAM (resistive RAM) crosspoint arrays. Visualizing 3D constructions could be a problem for the human mind: this can be manner a lot of these chapters comprise loads of bird’s-eye perspectives and go sections alongside the three axes.

The moment a part of the booklet is dedicated to different vital points, akin to complicated packaging know-how (i.e. TSV in bankruptcy nine) and blunder correction codes, that have been leveraged to enhance flash reliability for many years. bankruptcy 10 describes the evolution from legacy BCH to the latest LDPC codes, whereas bankruptcy eleven bargains with essentially the most fresh developments within the ECC box. final yet now not least, bankruptcy 12 seems at 3D flash thoughts from a approach perspective.

Is 14nm the final step for planar cells? Can a hundred layers be built-in in the related piece of silicon? Is four bit/cell attainable with 3D? Will 3D be trustworthy adequate for firm and datacenter purposes? those are a few of the questions that this publication is helping answering via delivering insights into 3D flash reminiscence layout, technique know-how and applications.

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Schedule delays in this industry are very costly since a particular SSD product line usually aligns with the lowest cost NAND available for a targeted timeframe, and that in turn governs architectural choices like ECC strength, DRAM interface, etc. Thus, if a controller has a revision, it would take an additional 6– 9 months and cause the SSD to perhaps be misaligned to the lowest cost NAND node that lasts only 12–15 months. This exquisite and narrow planning windows can be avoided with a flexible controller architecture capable of supporting multiple NAND process technology nodes and DRAM interfaces.

As higher monolithic densities are introduced in successive 3D NAND generations, one can predict there will be a split in the requirements for NAND component technologies for lower performance and higher capacity applications (in comparison to typical NAND specs, even lower performance NAND will be 100’s of times faster than HDD’s in performance) versus lower density but performance oriented applications. More on this in the next section. While this author does not believe that HDD will be completely replaced, the technical superiority of NAND-based solutions in power, performance, and reliability will have significant impact on reducing the number of HDD’s in many application segments and continue to force HDD’s towards higher capacities.

3 Floating Gate Versus Charge Trap Finally, in terms of NAND components, an interesting technology battle to watch is the use of either Floating Gate (FG) or Charge Trap (CT) technology for the fundamental NAND memory cell (Fig. 14). While most of the NAND vendors have chosen Charge trap, a notable exception is Micron/Intel joint venture, whose choice is Floating gate based NAND cell technology in their 3D NAND products. There is one set of industry process technology experts who argue that Floating Gate is a well-known technology with well understood failure modes that have been known and addressed for multiple generations.

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3D Flash Memories by Rino Micheloni

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